This invention relates to integrated circuit diagnosis, characterization and modification using charged particle beams.
Electron beam diagnostic systems have been a powerful tool for integrated circuit (IC) characterization and debug applications for many years. The well-known aspects of electron beam diagnostic systems include secondary electron imaging, circuit navigation using a built-in computer automated design (CAD) display, and voltage measurements from active circuits using voltage contrast principles. (See, for example, U.S. Pat. No. 4,706,019.) Electron beam diagnostic systems have traditionally been used on the frontside of an IC. The implementation of face-down or flip-chip IC packaging has created severe limitations for the use of electron beam diagnostic systems. An IC using flip-chip packaging has only the back-side (silicon substrate) of the IC exposed.
Three approaches currently exist for making electron beam measurements on the back-side of a flip-chip device: (1) circuit node access at probe points fabricated into the device (as described, for example, in U.S. Pat. No. 5,990,562); (2) circuit node access through exposure by focused ion beam after device fabrication (as described, for example, in U.S. Pat. No. 6,147,399); and (3) removing the silicon substrate entirely to enable access to the diffusion by wet chemical etching for back-side voltage measurement (as described, for example, in Yoshida, E., et al., Backside Electron Beam Testing Method, Proceedings of the LSI Testing Conference (1997), and U.S. Pat. No. 5,972,725). These approaches require either complicated device designs, specialized equipment, or time consuming device modifications after manufacturing.
The first approach relies on selecting the nodes to be probed at the device design phase. After device construction, the critical nodes for device debug or characterization are determined by electrical testing or other means. The nodes that are identified for probing may not have the necessary built-in probe points due to oversight during the device design. If a node needs to be probed after manufacturing, and a built-in probe point has not been designed-in, access to the node can be created using a focused ion beam. An alternative is to include probe points for every device node, which is impractical.
The second approach creates access to critical device nodes after manufacturing using a focused ion beam system. Using this method, nodes are identified by device testing or other means, and a focused ion beam system is used to remove the silicon substrate from the device back-side over a local area of the node to be probed. This method, while effective, can result in damage to the device by the focused ion beam system. Furthermore, the focused ion beam system can only expose one device node at a time. Creating access to multiple device nodes is a difficult, potentially damaging, and time-consuming process.
The third approach of removing the silicon substrate by wet chemical etch is only applicable to devices manufactured using silicon-on-insulator (SOI) technology or CMOS devices with an epitaxial layer. The SiO2 layer for an SOI device and the epitaxial layer for a CMOS device are used as barriers to stop the chemical etch reaction. This approach requires the effort and expense of using specialized equipment to deliver the necessary chemical agents. Once the substrate is completely removed, the problem of exactly locating the node of interest to be probed still remains.